Ferroelectric nonvolatile random access memory devices preserve the stored data state, even when the power supply signal is removed. The logic state of each memory cell generally is based on the electrical polarization of a ferroelectric capacitor, comprised of a ferroelectric material sandwiched between two conductive layers. When an electric field of sufficient magnitude is applied across the ferroelectric capacitor, the ferroelectric material will polarize in the direction of that electric field. The minimum voltage that must be applied across the capacitor in order to initiate reversal of the polarization state is defined as the coercive voltage.
It is well known that the direction of the polarization may be sensed by applying a voltage equal to or greater than the coercive voltage across a ferroelectric capacitor, and sensing the resulting current flow. If the polarity of the voltage applied is opposite to the polarization in a ferroelectric capacitor, the polarization of the ferroelectric capacitor will switch to the opposite state. If, on the other hand, the polarization in the ferroelectric capacitor is the same as the voltage applied, the ferroelectric capacitor will not switch polarization states. Since significantly more current results when a polarization switch occurs than when it does not, the resulting current can be used to determine the logic state of the ferroelectric capacitor. When reading is complete, the memory cells must be rewritten with their original logic state. This method is referred to as a “destructive read out” since the data stored in the ferroelectric capacitor is temporarily overwritten to a known value.
Also known in the art are various a “non-destructive read out” sensing techniques wherein the polarization stored in the ferroelectric capacitor is sensed without disturbing the stored polarization state. Such methods are generally based on detecting the capacitance of the ferroelectric capacitor by applying voltages less than the coercive voltage across the terminals of the ferroelectric capacitor.
Ferroelectric memory cells based on sensing the state of polarization of a ferroelectric capacitor, whether sensed destructively or non-destructively, result in a memory cell that requires additional transistor devices for selection of a particular cell within the memory array. Ferroelectric memories based on a class of devices known as ferroelectric FETs could offer significant memory cell size advantages, thereby decreasing the manufacturing cost dramatically. A ferroelectric FET known in the prior art is structurally identical to a metal-oxide-silicon field effect transistor (MOSFET) device with the oxide replaced by a ferroelectric material, as shown in FIG. 1. The state of polarization of the ferroelectric gives rise to an electric field, which shifts the turn-on threshold voltage of the device.
Although this device geometry has some attractive features, it suffers from several severe fabrication difficulties. One such difficulty is the incompatibility with CMOS integrated circuit process technologies. Ferroelectric memories are typically fabricated using a conventional CMOS semiconductor integrated circuit process with some additional process steps to fabricate the ferroelectric structure. The CMOS process generally provides the circuitry for sense amplifiers, decoders, and other circuitry needed for reading and writing. However, ferroelectric materials generally contain compounds and elements that are harmful to the operation of CMOS transistors, thereby risking contamination of the CMOS process facilities. For this reason, ferroelectric deposition is generally designed to be one of the last steps, which can be performed outside the main CMOS processing facility. However, this is generally not an option when producing a ferroelectric FET.
Another incompatibility between the CMOS process and ferroelectric fabrication is the conflicting effects of hydrogen exposure. It is known that hydrogen anneal steps are required in a stable CMOS process in order to reduce surface states. There are numerous sources of hydrogen in a CMOS process including tungsten plugs, inter-level dielectric oxides, alloy steps, passivation deposition, and plastic packaging of the integrated circuit. However, studies have also shown that when a ferroelectric material is exposed to hydrogen, the amount of switching charge degrades. Therefore, the process flow must generally be designed to shield the ferroelectric material from hydrogen while still exposing CMOS devices to hydrogen.
Another fabrication difficulty is diffusion of the ferroelectric material into the silicon causing inadvertent doping of the channel region and uncontrolled threshold voltage shifts of the ferroelectric FET. For example, the element bismuth (Bi) in the typical ferroelectric material SBT (strontium bismuth tantalate) can act as an n-type dopant. Since the sensing circuitry is designed with certain assumptions regarding the turn-on threshold of the ferroelectric FET, such inadvertent doping could result in an incorrect detection of the polarization state.
During thermal treatments that are part of the ferroelectric fabrication process, a thin layer of silicon dioxide generally grows at the silicon/ferroelectric interface due to oxygen exposure. The resulting structure can be viewed as a capacitor comprised of the silicon dioxide in series with a capacitor comprised of the ferroelectric material. Since the dielectric constant of silicon dioxide is low compared to typical ferroelectric materials by orders of magnitude, even an exceedingly thin layer of silicon dioxide will cause the voltage between the semiconductor layer and the top electrode to be divided so that the great majority of the voltage drops across the silicon dioxide layer. The remaining voltage across the ferroelectric material is then typically less than coercive voltage, resulting in slow or even non-existing switching properties.
Another problem in forming a high quality silicon/ferroelectric interface is the mismatch of lattice constants and thermal expansions. Such mismatch gives rise to significant stress on the ferroelectric/silicon interface, creating undesired charge traps and adherence issues.
Attempts to solve some of the ferroelectric/silicon interface problems in the prior art include forming a dielectric layer between the silicon substrate and the ferroelectric material, as shown in FIG. 2. This technique is generally not adequate, however. In order to apply a voltage higher than the coercive voltage across the ferroelectric layer, the dielectric constant of the dielectric material forming the dielectric layer must be very high. Compatible linear dielectric materials rarely have dielectric constants greater than 50, which is still more than an order of magnitude less than the dielectric constant of a typical ferroelectric material. When limited to these dielectric materials, the characteristics of the silicon/dielectric interface, though generally an improvement over the ferroelectric/silicon interface, is still inadequate.
In addition to these fabrication difficulties, ferroelectric FETs are known to suffer from poor retention of the logic state stored due to charge injection at the gate electrode/ferroelectric boundary. A high density of free charge accumulates on the surface of the electrode compensating the electric field generated by the polarization fields within the ferroelectric material. Because this accumulation of free charge occurs over a very short distance in the surface of the conductor, a high electric field is generated at electrode/ferroelectric boundary. The field strength is generally sufficiently high in order to inject charge into the ferroelectric material. This injected charge then obscures the electric field generated by the ferroelectric polarization, thereby decreasing the total electric field as seen from the silicon/ferroelectric interface. This compensation does not necessarily alter the flow of current resulting from polarization reversal, and so memory cells based on a ferroelectric capacitor are not typically affected. However, the decrease in total electric field will result in a turn-on threshold shift of a ferroelectric FET, which could result in an incorrect detection of the polarization state. When there is no dielectric material between the ferroelectric layer and the substrate, this charge injection phenomenon can occur on the ferroelectric/substrate interface as well.
As a result of problems introduced by these fabrication and device issues, memory cells based on ferroelectric FET have shown slow switching speeds, high operating voltages, and poor memory retention characteristics.